The present invention relates generally to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with specialized channel regions.
Integrated circuits (ICs), such as, ultra-large-scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed above a channel region and between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-inducted barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region just below the top surface of the substrate to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. With the silicon dioxide spacers in place, the substrate is doped a second time to form deep source and drain regions. During formation of the deep source and drain regions, further doping of the source and drain extensions is inhibited due to the blocking characteristic of the silicon dioxide spacers. The deep source and drain regions are necessary to provide sufficient material to connect contacts to the source and drain regions.
As transistors become smaller, it is desirous to increase the charge carrier mobility in the channel region. Increasing charge carrier mobility increases the switching speed of the transistor. Channel regions formed from materials other than silicon have been proposed to increase charge carrier mobility. For example, conventional thin film transistors which typically utilize polysilicon channel regions have been formed on a silicon germanium (Sixe2x80x94Ge) epitaxial layer above a glass (SiO2) substrate. The Sixe2x80x94Ge epitaxial layer can be formed by a technique in which a semiconductor thin film, such as, an amorphous silicon hydride (a-Si:H), an amorphous germanium hydride (a-Ge:H) or the like is melted and crystallized by the irradiation of pulse laser beams.
In a bulk type device, such as, a metal oxide semiconductor field effect transistor (MOSFET), the use of Sixe2x80x94Ge materials could be used to increase charge carrier mobility, especially hole-type carriers. A tensile strained silicon channel region, such as, a silicon channel containing germanium, can have carrier mobility 2-5 times greater than a conventional Si channel region due to reduced carrier scattering and due to the reduced mass of holes in the germanium-containing material. According to conventional Sixe2x80x94Ge formation techniques for bulk-type devices, a dopant implant molecular beam epitaxy (MBE) technique forms a Sixe2x80x94Ge epitaxial layer. However, the MBE technique requires very complicated, very expensive equipment and is not feasible for mass production of ICs.
Thus, there is a need for an integrated circuit or electronic device that includes channel regions with higher channel mobility. Further still, there is a need for transistors with a thin Sixe2x80x94Ge channel region and deep source and drain regions. Even further still, there is a need for a method of manufacturing a transistor having a thin Sixe2x80x94Ge channel region in a semiconductor substrate. Yet further, there is a need for a double gate transistor having a silicon/germanium channel. Yet even further, there is a need for an effluent method of manufacturing a double gate transistor having a channel containing germanium.
An exemplary embodiment relates to a method of manufacturing an integrated circuit on a substrate. The method includes providing a first amorphous semiconductor layer above a top surface of the substrate, annealing the first amorphous semiconductor layer to form a first crystallized layer, providing a second amorphous semiconductor layer including germanium above the first crystallized layer. The method also includes annealing the second amorphous semiconductor layer to form a second crystallized layer, providing a third amorphous semiconductor layer above the second crystallized layer, annealing the third amorphous semiconductor layer to form a third crystallized layer, providing a gate structure above the third crystallized layer, and doping the first, second and third crystallized layers. The first, second and third crystallized layers are doped at a source location and a drain location to form a source region and a drain region.
Another exemplary embodiment relates to a transistor. The transistor includes a first gate conductor, a first dielectric layer, a first silicon layer, a silicon germanium layer, a second silicon layer, and a second dielectric layer. A first gate conductor is disposed above a top surface of a substrate. The first gate dielectric layer is disposed below the first gate conductor and above the top surface of the substrate. The first silicon layer is disposed below the first dielectric layer and above the top surface of the substrate, and the silicon germanium layer is disposed above the top surface and below the first silicon layer. The second silicon layer is disposed above the top surface and below the silicon germanium layer. The second dielectric layer is disposed above the top surface and below the second silicon layer.
Another exemplary embodiment relates to a process of forming a transistor having a semiconductor germanium channel region above a top surface of a substrate. The process includes providing a dielectric layer above a top surface of the substrate, forming a gate conductor below the top surface of the substrate, providing a first amorphous semiconductor layer above the dielectric layer. The process further includes forming a first crystallized layer from the first amorphous semiconductor layer, providing a second amorphous semiconductor layer including germanium above the first crystallized layer, forming a second crystallized layer from the second amorphous semiconductor layer, and providing a third amorphous semiconductor layer above the second crystallized layer. The process further includes forming a third crystallized layer from the third amorphous semiconductor layer, and providing a gate structure above the third crystallized semiconductor layer.